As an electronic computer has recently become larger in scale and higher in performance, a quick response to faults is required. A lot of emphasis is put on a totally self-checking checker detecting the faults of a) logical circuit and b) checker during the execution of the system. As a result, a design method of the totally self-checking itself has been proposed with regard to the logical circuit outputting the M-out-of-2M code.
The M-out-of-2M code is a set of 2-value vectors having a logical value "1" of the M bits in 2M bits. The M-out-of-2M code has the largest number of code words in uni-directional error-detecting codes. It is recomended from the standpoint of checking speed that this totally self-checking checker, from input to output, be composed of a small number of logical gate levels. It is assumed at present that a 2-level logical gate design is a design having the least number of gate levels.
The totally self-checking checker in question is equipped with a one-level AND gate group inputting per code words of the code. The output of an AND gate group is input to an OR gate per the partial set with the code words divided into two code word sets. In the conventional totally self-checking checker mentioned above, the AND gates corresponding to all the code words and two OR gates inputting them are required. The total number of gates is {all the code words+2}.
It is required that all the code words is used to test this totally self-checking checker.